Tuesday, May 29, 2012

RTL Viewer Update

State of the Viewer

Things are progressing slightly well with wxDebuggy, it now does a half-decent job of drawing some verilog modules and the wiring between them -- and all this while limiting the number of crossovers!

As mentioned before, I wasn't too happy with the wire-crossing reduction results when using a straight version of the Sugiyama et al algorithm. The current revision of the RTL Viewer improves the crossover reduction using two techniques:

  1. The layer reordering stage of the Sugiyama et al algorithm was tweaked using ideas found here (SFvHM09). With this tweak, the layout algorithm now knows that modules have ports and that these ports are in a fixed order.

  2. The orthogonal wire routing algorithm use 'Greedy Assign' to place the vertical line segments of each wire to a unique track between the layers. This idea comes from (EGB04).

Stuff to Fix for 'Dishwater' Tag

  • Y co-ordinate assignment of the modules should be improved.
  • Long dummy edges should be kept straight.
  • Clock/reset-like signals that go to multiple modules in multiple layers need to be handled better.
  • Feedback wires are not drawn all that well.

Misc worries

  • RTL parser is very slow. The files I test on have basic RTL and wiring, and there are only about 12 of them, but it takes around 3 seconds for my desktop to parse them and build the necessary data structures.
  • Greedy assign may not be enough for more involved circuits - I may need to add the 'Sifting' bit too.

References

2 comments:

Amal Khailtash said...

Great looking tool!

I tried to find your contact info, but I could not. So I opened a bug report on your github page:

https://github.com/Harnesser/wxDebuggy/issues/1

-- Amal

Marty said...

Thanks for taking interest. The program is nowhere near finished yet - it can only do small ccts empty ccts! I haven't worked much on it because I'm off learning how to write a Verilog parser in C.